This invention relates in general to integrated circuit ("IC") test systems and in particular, to an adaptable wafer probe assembly for testing a variety of ICs having different power and/or ground bond pad configurations.
Integrated circuits, especially those of the so-called application specific type, may have any one of a number of different power and/or ground bond pad configurations. FIG. 1A illustrates, as a simplified example, a top plan view of one such IC die 100, wherein bond pads 1-16 provide external device electrical connection means to the active circuitry 50 of the IC die 100. Depending upon the functionality and layout of the active circuitry 50, some of the bond pads will be assigned by the layout designer to communicate input and/or output signals "S" to and/or from the active circuitry 50, at least one bond pad will be assigned to provide power "P" to the active circuitry 50, and at least one bond pad will be assigned to provide an external ground connection "G" for the active circuitry 50.
FIGS. 1B-1D illustrate examples of such possible bond pad assignments (also referred to herein as "configurations") for the IC die example of FIG. 1A. FIG. 1B illustrates one example where opposing corner bond pads 1 and 9 are assigned to be power "P" bond pads, opposing corner bond pads 5 and 13 are assigned to be ground "G" bond pads, and the remaining bond pads are assigned to be input and/or output signal "S" bond pads; FIG. 1C illustrates a second example where the power "P" and ground "G" bond pad assignments have been reversed; and FIG. 1D illustrates a third example where the power "P" and ground "G" bond pad assignments are not in the corner bond pads.
When testing the integrated circuit die 100, it is desirable to minimize the noise level (also referred to as "bounce") on the power and ground lines to the IC die 100. FIGS. 2A and 2B illustrate, as examples, circuits for reducing such noise on the power and ground lines, PL and GL, respectively, wherein in FIG. 2A, a voltage source Vdd is shown providing power over power line PL to the IC die 100 at bond pad P, and in FIG. 2b, a ground reference GND' is shown being provided over ground line GL to the IC die 100 at bond pad G. To prevent noise generated on the power and ground lines, PL and GL, respectively, from entering and affecting the proper operation of IC die 100, decoupling capacitors 20 and 22 are respectively connected at nodes 24 and 26 to the power and ground lines PL and GL, thereby shunting noise generated on these lines to ground GND.
As a practical matter, however, some of the noise generated on the power and ground lines, PL and GL, respectively, will still enter the IC die 100. For example, noise generated between node 24 and bond pad P on the power line PL will not be filtered out by decoupling capacitor 20, and noise generated between node 26 and bond pad G on the ground line GL will not be filtered out by decoupling capacitor 22. Accordingly, to minimize such noise, it is preferable to connect decoupling capacitors 20 and 22 as close as possible to bond pads P and G, respectively.